The present invention relates generally to the field of testing of integrated circuit devices and, more particularly, to a method of testing field programmable gate array resources and identifying faulty field programmable gate array resources.
A field programmable gate array (FPGA) is a type of integrated circuit consisting of an array of programmable logic blocks interconnected by a programmable routing network and programmable input/output cells. Programming of the logic blocks, the routing network and the input/output cells is selectively completed to make the necessary interconnections that establish one configuration thereof to provide the desired system operation/function for a particular application.
The present inventors have recently developed methods of built-in self-testing the array of programmable logic blocks and the programmable routing resources in FPGAs at the device, board and system levels. These methods are set out in detail in U.S. Pat. Nos. 5,991,907, 6,003,150, and 6,108,806 and pending U.S. application Ser. No. 09/109,123. The full disclosures in these patents and patent applications are incorporated herein by reference.
In addition to these off-line testing methods, the present inventors have also recently developed methods of on-line testing and fault tolerant operation of FPGAs. These methods are set out in detail in pending U.S. application Ser. Nos. 09/261,776, 09/405,958, 09/406,219, and 09/611,449. The full disclosure of these patent applications is also incorporated herein by reference.
On-line testing and fault tolerant operation of FPGAs is most important in high-reliability and high-availability applications, such as, space missions, telecommunication network routers, or remote equipment in which adaptive computing systems often rely on reconfigurable hardware to adapt system operation. In such applications, the FPGA hardware must work continuously and simply cannot be taken off-line for testing, maintenance, or repair.
When a fault is detected in the resources of the FPGA hardware of these systems during testing, the faulty resource must be quickly identified and the remaining FPGA resources reconfigured to replace the faulty resource, or a faulty mode of operation of the identified resource diagnosed in order to allow continued operation of the faulty resource in a diminished capacity. Therefore, the steps of testing and identifying FPGA resources, and diagnosing faulty modes of operation in the faulty identified resources must be performed concurrently with normal system operation.
In accordance with the present invention, resources of a field programmable gate array (FPGA) determined to be faulty during testing may now be quickly identified and the remaining FPGA resources reconfigured to replace the faulty resource, or a faulty mode of operation of the identified resource diagnosed in order to allow its continued operation in a diminished capacity, during normal on-line operation of the FPGA. Specifically, when a fault is detected in a group of FPGA resources under test, the FPGA resources are reconfigured such that the resources within the group of resources under test are subdivided and grouped with additional FPGA resources known to be fault free for further testing. Dependent upon the result of the further testing, the steps of reconfiguring and further testing are repeated until the detected faulty resource is identified. Once the faulty resource is identified, the remaining FPGA resources are reconfigured to replace the faulty resource in order to provide fault tolerant operation of the FPGA.
On-line testing of the FPGA resources is accomplished by configuring the FPGA into a working area and an initial self-testing area. The working area maintains normal operation of the FPGA throughout testing. Within the initial and subsequent self-testing areas, however, the FPGA resources are tested for faults. It is initially presumed that all of the resources of the FPGA are fault-free as determined through manufacturing testing.
Within the initial self-testing area, test patterns are generated and applied to FPGA resources selected for testing. Outputs of a first group of FPGA resources under test, e.g., programmable logic blocks, programmable routing network resources, or a combination of both, are preferably compared to outputs of a second group of equivalently configured FPGA resources under test. Based on a comparison of the outputs of the groups of FPGA resources under test, fault status data is generated.
When the fault status data indicates the detection of a fault in the groups of FPGA resources under test, the resources within the initial self-testing area of the FPGA are reconfigured into subsequent groups of FPGA resources under test for further testing in order to identify the faulty resource. As indicated above, the group of FPGA resources under test where the fault was detected is subdivided and its resources grouped with additional FPGA resources known to be fault free to form subsequent groups of FPGA resources for further testing in the manner described above.
In accordance with another aspect of the present inventive method, the initial self-testing area of the FPGA is preferably configured to include groups of FPGA resources, or self-testing tiles, for testing the programmable logic blocks. Each self-testing tile preferably includes programmable logic blocks configured to function as a test pattern generator, an output response analyzer, and equivalently configured programmable logic blocks under test. The initial self-testing area of the FPGA may be divided into any number of equivalently configured self-testing tiles so long as each testing tile contains a sufficient amount of FPGA resources to complete testing. Advantageously, this allows for concurrent testing of the programmable logic blocks in several testing tiles within the self-testing area, thus reducing the overall test time and fault latency.
During testing, test patterns are generated by the test pattern generator and applied to the programmable logic blocks under test. Outputs of a first programmable logic block under test are compared to outputs of a second equivalently configured programmable logic block under test by the output response analyzer. Based on the comparison of the outputs of the programmable logic blocks under test, fault status data is generated.
When the fault status data indicates the detection of a fault in one of the logic blocks of a testing tile, the resources within the initial self-testing area of the FPGA are reconfigured into subsequent self-testing tiles in order to identify the faulty programmable logic block. Specifically, the logic blocks in the testing tile where the fault is originally detected are subdivided and grouped with additional logic blocks known to be fault-free to form the subsequent testing tiles wherein the logic blocks are further tested in the manner described above. Dependent upon the subsequent fault status data, the programmable logic blocks in the subsequent self-testing tiles may be further subdivided, grouped, and tested until the detected faulty logic block is identified. Once the faulty logic block is identified, the remaining FPGA resources are reconfigured to replace the faulty logic block in order to provide fault tolerant operation. Alternatively, diagnostic testing of the identified logic block is conducted in order to determine a faulty mode of operation.
Based on the fault status data generated during diagnostic testing, partially faulty logic blocks may be reconfigured to perform only non-faulty functions or modes of operation and further utilized. By reconfiguring partially faulty logic blocks to avoid all modes of operation affected by the fault, the partially faulty logic blocks are allowed to continue to operate in a progressively diminished, although acceptable, capacity for specific operating modes.
To test the programmable routing resources of the FPGA, test patterns are generated and propagated along groups of wires under test. Output patterns of a first group of wires under test are preferably compared to output patterns of a second group of wires under test receiving the same patterns. In order to achieve a complete test of the programmable routing resources within the initial self-testing area, the groups of wires under test include wire segments of varying lengths interconnected by configuration interconnect points, and possibly programmable logic blocks configured as identify functions. Advantageously, this allows both global routing resources between programmable logic blocks and local routing resources leading to each programmable logic block to be tested. As indicated above, the output patterns of the groups of wires under test are compared and test result data generated.
In order to minimize the number of reconfigurations of the FPGA under test and reduce overall testing time and fault latency, parallel testing of the programmable routing resources are preferably utilized. Specifically, comparisons of the output patterns of segments of the groups of wires under test may be made at several locations along the groups of wires under test utilizing a plurality of FPGA resources configured as output response analyzers producing fault status data for each segment of the groups of wires under test.
When the fault status data indicates the detection of a fault in one of the groups of wires under test, the resources within the groups of wires under test are reconfigured into subsequent groups of wires under test in order to identify the faulty routing resource. Specifically, the resources in the groups of wires under test where the fault is originally detected are subdivided and grouped with additional resources known to be fault-free to form the subsequent groups of wires under test wherein the routing resources are further tested in the manner described above. Dependent upon the subsequent fault status data, the routing resources in the subsequent groups of wires under test may be further subdivided, grouped, and tested until the detected faulty routing resource is identified. Once the faulty routing resource is identified, the remaining FPGA resources are reconfigured to replace the faulty resource in order to provide fault tolerant operation.
Upon completion of testing each of the FPGA resources located within the initial self-testing area, identifying the faulty resources, and diagnosing the faulty logic blocks, the FPGA under test is reconfigured so that a portion of the working area becomes a subsequent self-testing area, and the initial self-testing area, reconfigured to avoid faulty resources, becomes a portion of the working area. In other words, the self-testing area roves around the FPGA under test repeating the steps of testing and reconfiguring within the self-testing areas until each portion of the FPGA under test, is reconfigured as a subsequent self-testing area, tested, and detected faults within the FPGA resources diagnosed. As noted above, the present method of testing allows for normal operation of the FPGA under test to continue within the working area uninterrupted by the testing conducted within the self-testing areas.
An apparatus for testing the resources of the FPGA under test during normal on-line operation includes a test and reconfiguration controller in communication with the FPGA under test for: (a) configuring the FPGA under test into an initial self-testing area and a working area, the working area maintaining normal operation of the FPGA; (b) testing the resources located within the initial self-testing area for faults; (c) reconfiguring the resources located within the initial self-testing area for further testing in order to identify the faulty resource; (d) further testing resources located within the reconfigured self-testing area; and (e) repeating the steps of reconfiguring and further testing until the faulty resource is identified. The testing apparatus further includes a storage medium in communication with the test and reconfiguration controller for storing a plurality of test configurations, and usage and fault status data for each FPGA resource.
An FPGA in accordance with the present invention includes a plurality of programmable logic blocks and a plurality of programmable routing resources interconnecting the programmable logic blocks initially configured as an initial self-testing area for testing at least a portion of the programmable routing resources and/or programmable logic blocks for faults, and an initial working area for maintaining normal operation of the FPGA during testing. The portion of the programmable routing resources and/or programmable logic blocks located within the initial self-testing area are further subdivided and tested until the faulty programmable routing resource or programmable logic block is identified.